Field of Invention
The present invention relates to a power detector in which calibration is performed to minimize errors caused by a process variation and a temperature variation in a low supply voltage (VDD).
Description of Prior Art
Contents described below provide only background information related to embodiments of the present invention and do not describe the related art.
A conventional power detector (PD) illustrated in FIG. 1 serves to convert a voltage into a current domain in a first N-type amplifier (MN1) and a second N-type amplifier (MN2). The conventional PD may serve as a rectifier after combining two output currents of a first N-type amplifier (MN1) and a second N-type amplifier (MN2) in a first P-type amplifier (MP1). The conventional PD serves to apply an output thereof to a second P-type amplifier (MP2) and convert the output into a voltage domain using a first resistor (R1). Since an undesired high-frequency component still exists on a node when the PD converts the output into the voltage domain, the PD removes frequency components other than a direct current (DC) component using a resistive-capacitive (RC) low pass filter. Since an area of a capacitor is generally large in a complementary metal-oxide-semiconductor (CMOS) process when an RC filter is manufactured, the PD reduces an RC pole by increasing a size of a second resistor (R2). For example, a value of the first resistor (R1) may range from 500 kΩ to several MΩ.
A peak detector, a root-mean square (RMS) detector, or the like is used in a concept similar to the conventional PD. A main function of the PD is to minimize errors caused between an input and an output thereof when power or a peak voltage applied to the input is converted into a DC output voltage. In the PD, since a PD output value (PD_OUT) varies sensitively according to a process variation and a temperature variation, it is an important factor to control the PD output value (PD_OUT) in the PD. In the case of a peak detector, feed-back is performed so that a gain of a main amplifier of a PD becomes 1.
The peak detector charges electric charges to a capacitor while a signal is looking for a positive (+) peak by implementing a capacitor and a diode in an output node of the PD. The peak detector is fed back to have a structure in which a peak voltage value is found by reducing a rate at which the electric charges are discharged by the capacitor while the signal is looking for a negative (−) peak. Due to the above-described feedback structure, there is an advantage in that the peak detector may operate insensitive to the process variation and the temperature variation.
However, the peak detector has a structure in which it is difficult to infer the performance of the amplifier when being used in a range from several hundred MHz to several GHz and is difficult to have a wide input dynamic range at a low supply voltage (VDD). For example, when a supply voltage (VDD) of 1.2 V is used in the peak detector, the PD output value (PD_OUT) is limited to 400 mV within a range from 0.6 V to 1 V.
An RMS detector or a PD has a structure in which an input voltage is converted into a current interface using a metal-oxide-semiconductor (MOS), the current interface is rectified, and a PD output value (PD_OUT) of the voltage interface is then generated again using a resistor. Since the RMS detector or the PD processes in an input voltage current domain, there is an advantage in that the RMS detector or the PD operates at a high frequency. In the RMS detector or the PD, a restriction of 0.6 V for determining a minimum (MIN) voltage level of the PD output value (PD_OUT) for operating an amplifier of the above-described supply voltage (VDD) of 1.2 V disappears. Therefore, it is advantageous in that the RMS detector or the PD has a wide input dynamic range. However, since the RMS detector or the PD is sensitive to a GM variation of the input MOS transistor, it is difficult to ignore a temperature variation. Since resistance in a process of converting into a voltage domain by a resistor after rectification is changed by about ±15% in a CMOS process, a chip variation problem may occur.